Altera Transceiver PHY IP Core - Manual (Page 246)

Word
Addr
Bits R/W Register Name Description
0x085
[3] RW
rx_bitslip
Every time this register transitions from 0
to 1, the RX data slips a single bit.
To block: Word aligner.
[2] RW
rx_bytereversal_enable
When set, enables byte reversal on the RX
interface.
To block: Byte deserializer.
[1] RW
rx_bitreversal_enable
When set, enables bit reversal on the RX
interface.
To block: Word aligner.
[0] RW
rx_enapatternalign
When set in manual word alignment
mode, the word alignment logic begins
operation when this pattern is set.
To block: Word aligner.
SDC Timing Constraints
The SDC timing constraints and approaches to identify false paths listed for Stratix V Native PHY IP
apply to all other transceiver PHYs listed in this user guide. Refer to SDC Timing Constraints of Stratix V
Native PHY for details.
Related Information
SDC Timing Constraints of Stratix V Native PHY on page 12-74
This section describes SDC examples and approaches to identify false timing paths.
Dynamic Reconfiguration
As silicon progresses towards smaller process nodes, circuit performance is affected more by variations
due to process, voltage, and temperature (PVT). These process variations result in analog voltages that can
be offset from required ranges.
The calibration performed by the dynamic reconfiguration interface compensates for variations due to
PVT.
Each channel and each TX PLL have separate dynamic reconfiguration interfaces. The MegaWizard Plug-
In Manager provides informational messages on the connectivity of these interfaces. The following
example shows the messages for a single duplex channel parameterized for the 1.25 GIGE protocol.
Although you must initially create a separate reconfiguration interface for each channel and TX PLL in
your design, when the Quartus II software compiles your design, it reduces the number of reconfiguration
interfaces by merging reconfiguration interfaces. The synthesized design typically includes a reconfigura‐
tion interface for at least three channels because three channels share an Avalon-MM slave interface
which connects to the Transceiver Reconfiguration Controller IP Core. Conversely, you cannot connect
the three channels that share an Avalon-MM interface to different Transceiver Reconfiguration
Controller IP Cores. Doing so causes a Fitter error.
UG-01080
2015.01.19
SDC Timing Constraints 9-33
Custom PHY IP Core Altera Corporation
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