Altera Transceiver PHY IP Core User Manual
Page 337
Table 12-29: 10GBASE-R BER Checker Parameters
Parameter
Range
Description
Enable rx_10g_highber port
(10GBASE-R)
On/Off
When you turn this option On, the TX
10G PCS datapath includes the
rx_10g_
highber
output port. This signal is
asserted to indicate a BER of >10
4
. A
count of 16 errors in 125- m s period
indicates a BER > 10
4
. This signal is
only available for the 10GBASE-R
protocol.
Enable rx_10g_highber_clr_cnt port
(10GBASE-R)
On/Off
When you turn this option On, the TX
10G PCS datapath includes the
rx_10g_
highber_clr_cnt
input port. When
asserted, the BER counter resets to 0.
This signal is only available for the
10GBASE-R protocol.
Enable rx_10g_clr_errblk_count port
(10GBASE-R)
On/Off
When you turn this option On, the 10G
PCS includes the
rx_10g_clr_errblk_
count
input port. When asserted, error
block counter that counts the number of
RX errors resets to 0. This signal is only
available for the 10GBASE-R protocol.
64b/66b Encoder and Decoder
The 64b/66b encoder and decoder conform to the 10GBASE-R protocol specification as described in IEEE
802.3-2008 Clause-49. The 64b/66b encoder sub-block receives data from the TX FIFO and encodes the
64-bit data and 8-bit control characters to the 66-bit data block required by the 10GBASE-R protocol. The
transmit state machine in the 64b/66b encoder sub-block checks the validity of the 64-bit data from the
MAC layer and ensures proper block sequencing.
The 64b/66b decoder sub-block converts the received data from the descrambler into 64-bit data and 8-bit
control characters. The receiver state machine sub-block monitors the status signal from the BER
monitor. The following table describes the 64/66 encoder and decoder parameters.
Table 12-30: 64b/66b Encoder and Decoder Parameters
Parameter
Range
Description
Enable TX sync header error
insertion
On/Off
When you turn this option On, the 10G PCS records.
This parameter is valid for the Interlaken and
10GBASE-R protocols.
Enable TX 64b/66b encoder
On/Off
When you turn this option On, the 10G PCS
includes the TX 64b/66b encoder.
Enable TX 64b/66b encoder
On/Off
When you turn this option On, the 10G PCS
includes the RX 64b/66b decoder.
UG-01080
2015.01.19
10G PCS Parameters for Stratix V Native PHY
12-39
Stratix V Transceiver Native PHY IP Core
Altera Corporation