Altera Transceiver PHY IP Core - Manual (Page 250)

Implementa‐
tion
Number of
Lanes
Serialization
Factor
Worst-Case
Frequency
Combinational
ALUTs
Dedicated
Registers
Memory Bits
6 Gbps (8
Gbps
datapath)
1 32 or 40 607.16 113 93 0
6 Gbps (8
Gbps
datapath)
4 32 or 40 639.8 142 117 0
6 Gbps (8
Gbps
datapath)
10 32 or 40 621.89 193 171 0
3 Gbps (8
Gbps
datapath)
1 8, 10, 16, or 20 673.4 114 93 0
3 Gbps (8
Gbps
datapath)
4 8, 10, 16, or 20 594.88 142 117 0
3 Gbps (8
Gbps
datapath)
10 8, 10, 16, or 20 667.67 193 171 0
.
Parameterizing the Low Latency PHY
Complete the following steps to configure the Low Latency PHY IP Core in the MegaWizard Plug-In
Manager:
1. Under Tools > IP Catalog, select Stratix V as the device family.
2. Under Tools > IP Catalog > Interface Protocols > Transceiver PHY, select Low Latency PHY.
3. Use the tabs on the MegaWizard Plug-In Manager to select the options required for the protocol.
4. Refer to the following topics to learn more about the parameters:
UG-01080
2015.01.19
Parameterizing the Low Latency PHY 10-3
Low Latency PHY IP Core Altera Corporation
Send Feedback