Altera Transceiver PHY IP Core User Manual
Page 86
Signal Name
Direction
Description
reconfig_from_xcvr
[(
Output
Reconfiguration signals to the Reconfiguration
Design Example.
number of reconfiguration interfaces.
rc_busy
Input
When asserted, indicates that reconfiguration is in
progress.
lt_start_rc
Output
When asserted, starts the TX PMA equalization
reconfiguration.
main_rc[5:0]
Output
The main TX equalization tap value which is the
same as V
OD
. The following example mappings to
the V
OD
settings are defined:
• 6'b111111: FIR_MAIN_12P6MA
• 6'b111110: FIR_MAIN_12P4MA
• 6'b000001: FIR_MAIN_P2MA
• 6'b000000: FIR_MAIN_DISABLED
post_rc[4:0]
Output
The post-cursor TX equalization tap value. This
signal translates to the first post-tap settings. The
following example mappings are defined:
• 5'b11111: FIR_1PT_6P2MA
• 5'b11110: FIR_1PT_6P0MA
• 5'b00001: FIR_1PT_P2MA
• 5'b00000: FIR_1PT_DISABLED
pre_rc[3:0]
Output
The pre-cursor TX equalization tap value. This
signal translates to pre-tap settings. The following
example mappings are defined:
• 4'b1111: FIR_PRE_3P0MA
• 4'b1110: FIR_PRE_P28MA
• 4'b0001: FIR_PRE_P2MA
• 4'b0000: FIR_PRE_DISABLED
tap_to_upd[2:0]
Output
Specifies the TX equalization tap to update to
optimize signal quality. The following encodings are
defined:
• 3'b100: main tap
• 3'b010: post-tap
• 3'b001: pre-tap
seq_start_rc
Output
When asserted, starts PCS reconfiguration.
4-30
Dynamic Reconfiguration Interface Signals
UG-01080
2015.01.19
Altera Corporation
Backplane Ethernet 10GBASE-KR PHY IP Core with Early Access FEC Option