Altera Transceiver PHY IP Core - Manual (Page 245)

Custom PCS
Table 9-25: Custom PCS
Word
Addr
Bits R/W Register Name Description
0x080 [31:0] RW Lane or group number Specifies lane or group number for
indirect addressing, which is used for all
PCS control and status registers. For
variants that stripe data across multiple
lanes, this is the logical group number.
For non-bonded applications, this is the
logical lane number.
0x081
[5:1] R
rx_bitslipboundaryselect
out
This is an output from the bit slip word
aligner which shows the number of bits
slipped.
From block: Word aligner.
[0] R
rx_phase_comp_fifo_error
When set, indicates an RX phase
compensation FIFO error.
From block: RX phase Compensation
FIFO
0x082 [0] RW
tx_phase_comp_fifo_error
When set, indicates an TX phase
compensation FIFO error.
From block: TX phase Compensation
FIFO
0x083
[5:1] RW
tx_bitslipboundary_
select
Sets the number of bits that the TX bit
slipper needs to slip.
To block: Word aligner.
[0] RW
tx_invpolarity
When set, the TX interface inverts the
polarity of the TX data.
To block: 8B/10B encoder.
0x084 0 RW
rx_invpolarity
When set, the RX channels inverts the
polarity of the received data.
To block: 8B/10B decoder.
9-32 Custom PCS
UG-01080
2015.01.19
Altera Corporation Custom PHY IP Core
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