Altera Transceiver PHY IP Core User Manual
Page 67
In this figure, the colors have the following meanings:
• Green-Altera- Cores available Quartus II IP Library, including the 1G/10Gb Ethernet MAC, the Reset
Controller, and Transceiver Reconfiguration Controller.
• Orange-Arbitration Logic Requirements. Logic you must design, including the Arbiter and State
10GBASE-KR PHY Arbitration Logic Requirements
on page 4-14 and
10GBASE-KR PHY State Machine Logic Requirements
on page 4-15 for a description of this logic.
• White - 1G,10G and AN/LT settings files that you must generate. Refer to
on page 4-49 for more information.
• Blue-The 10GBASE-KR PHY IP core available in the Quartus II IP Library.
Figure 4-2: Detailed 10GBASE-KR PHY IP Core Block Diagram
58
1G/10Gb
Ethernet
MAC
Backplane-KR or 1G/10Gb Ethernet PHY MegaCore Function
Backplane-KR or 1G/10Gb Ethernet PHY MegaCore Function
Backplane-KR or 1G/10Gb Ethernet PHY MegaCore Function
Native PHY Hard IP
TX
Serial
Data
RX
Serial
Data
322.265625 or
644.53125
Ref Clk
62.5 or 125
Ref Clk
ATX/CMU
TX PLL
For
10 GbE
ATX/CMU
TX PLL
For 1 GbE
1.25 Gb/
10.3125 Gb
Hard PMA
Link
Status
S
Reset
Controller
State
Machine
Arbiter
Rate Change Requests
AN & LT Requests
Transceiver
Reconfig
Controller
10 Gb
Ethernet
Hard PCS
Cntl &
Status
RX GMII Data
TX GMII Data
@ 125 MHz
RX XGMII Data
TX XGMII Data
Shared Across Multiple Channels
Can Share
Across Multiple
Channels
@156.25 MHz
1 GIGE
PCS
1G/10Gb
Ethernet
MAC1G/10Gb
Ethernet
MAC
1G
AN/LT
10G
FEC
1 Gb
Ethernet
Standard
Hard PCS
AN & LT
Soft
10G PCS
& FEC
Sequencer
As this figure illustrates, the 10GBASE-KR PHY is built on the Native PHY and includes the following
additional blocks implemented in soft logic to implement Ethernet functionality defined in Clause 72 of
IEEE 802.3ap-2007.
Link Training (LT), Clause 72
This module performs link training as defined in Clause 72. The module facilitates two features:
• Daisy-chain mode for non-standard link configurations where the TX and RX interfaces connect to
different link partners instead of in a spoke and hub or switch topology.
UG-01080
2015.01.19
10GBASE-KR PHY IP Core Functional Description
4-11
Backplane Ethernet 10GBASE-KR PHY IP Core with Early Access FEC Option
Altera Corporation