Altera Transceiver PHY IP Core User Manual
Page 319
Status Condition
Protocol
Mapping of Status Flags to RX Data
Value
Deletion
Basic double width
Serial RapidIO double width
RXD[62:62] = rx_
rmfifostatus[1:0]
, or
RXD[46:45] = rx_rmfifos-
tatus[1:0]
, or
RXD[30:29] = rx_
rmfifostatus[1:0]
, or
RXD[14:13] = rx_rmfifos-
tatus[1:0]
2'b01
All other protocols
Depending on the FPGA fabric to
PCS interface width either:
RXD[46:45] = rx_rmfifos-
tatus[1:0]
, or
RXD[14:13] = rx_rmfifos-
tatus[1:0]
2'b01
Word Aligner and Bit-Slip Parameters
The word aligner aligns the data coming from RX PMA deserializer to a given word boundary. When the
word aligner operates in bit-slip mode, the word aligner slips a single bit for every rising edge of the bit
slip control signal. The following table describes the word aligner and bit-slip parameters.
Table 12-17: Word Aligner and Bit-Slip Parameters
Parameter
Range
Description
Enable TX bit-slip
On/Off
When you turn this option On, the PCS
includes the bit-slip function. The outgoing
TX data can be slipped by the number of bits
specified by the
tx_bitslipboundarysel
control signal.
Enable tx_std_bitslipboundarysel
control input port
On/Off
When you turn this option On , the PCS
includes the optional
tx_std_bitslipboun-
darysel
control input port.
UG-01080
2015.01.19
Standard PCS Parameters for the Native PHY
12-21
Stratix V Transceiver Native PHY IP Core
Altera Corporation