Altera Transceiver PHY IP Core User Manual
Page 217
Name
Value
Description
Bonding mode
Non-bonded or x1
Bonded or xN
fb_compensation
Select Non-bonded or x1 to use separate clock
sources for each channel. (This option is available for
Cyclone V and Arria V devices.) If one PLL drives
multiple channels, PLL merging is required. During
compilation, the Quartus II Fitter, merges all the
PLLs that meet PLL merging requirements. Refer to
Merging TX PLLs In Multiple Transceiver PHY
on page 16-57 to observe PLL merging
rules.
Select Bonded or xN to use the same clock source for
up to 6 channels in a single transceiver bank,
resulting in reduced clock skew. You must use
contiguous channels when you select ×N bonding. In
addition, you must place logical channel 0 in either
physical channel 1 or 4. Physical channels 1 and 4 are
indirect drivers of the ×N clock network.
Select fb_compensation (feedback compensation) to
use the same clock source for multiple channels
across different transceiver banks to reduce clock
skew. (This option is only available for Stratix V
devices.)
For more information about bonding, refer to
"Transmitter Clock Network" in
in volume 2 of the
Arria V Device Handbook.
For more information about bonding, refer to
"Transmitter Clock Network" in
in volume 2 of the
Cyclone V Device Handbook.
For more information about bonding, refer to
"Bonded Channel Configurations Using the PLL
in volume 2 of the
Stratix V Device Handbook.
FPGA fabric transceiver
interface width
8,10,16,20, 32,40
Specifies the total serialization factor, from an input
or output pin to the MAC-layer logic.
9-4
General Options Parameters
UG-01080
2015.01.19
Altera Corporation
Custom PHY IP Core