Altera Transceiver PHY IP Core - Manual (Page 612)

Assign To
Pin - RX serial data
XCVR_RX_LINEAR_EQUALIZER_CONTROL
Pin Planner and Assignment Editor Name
Receiver Linear Equalizer Control
Description
Static control for the continuous time equalizer in the receiver buffer. The equalizer has 16 settings from
0–15 corresponding to the increasing AC gain.
Options
1 –16
Assign To
Pin - RX serial data
XCVR_RX_COMMON_MODE_VOLTAGE
Pin Planner and Assignment Editor Name
Receiver Buffer Common Mode Voltage
Description
Receiver buffer common-mode voltage.
Note: Contact Altera for using this assignment.
Related Information
How to Contact Altera on page 21-42
XCVR_RX_ENABLE_LINEAR_EQUALIZER_PCIEMODE
Pin Planner and Assignment Editor Name
Receiver Linear Equalizer Control (PCI Express)
Description
If enabled equalizer gain control is driven by the PCS block for PCI Express. If disabled equalizer gain
control is determined by the
XCVR_RX_LINEAR_EQUALIZER_SETTING
Options
TRUE
FALSE
19-18 XCVR_RX_LINEAR_EQUALIZER_CONTROL
UG-01080
2015.01.19
Altera Corporation Analog Parameters Set Using QSF Assignments
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