Altera Transceiver PHY IP Core - Manual (Page 158)

Name Direction Description
rx_errdetect[7:0]
Output Transceiver 8B/10B code group violation or disparity
error indicator. If either signal is asserted, a code group
violation or disparity error was detected on the associated
received code group. Use the
rx_disperr
signal to
determine whether this signal indicates a code group
violation or a disparity error. The
rx_errdetect
signal is
2 bits wide per channel for a total of 8 bits per XAUI link.
rx_patterndetect[7:0]
Output Indicates that the word alignment pattern programmed
has been detected in the current word boundary. The
rx_
patterndetect
signal is 2 bits wide per channel for a
total of 8 bits per XAUI link.
rx_rmfifodatadeleted[7:0]
Output Status flag that is asserted when the rate match block
deletes a ||R|| column. The flag is asserted for one clock
cycle per deleted ||R|| column.
rx_rmfifodatainserted[7:0]
Output Status flag that is asserted when the rate match block
inserts a ||R|| column. The flag is asserted for one clock
cycle per inserted ||R|| column.
rx_runningdisp[7:0]
Output Asserted when the current running disparity of the 8B/
10B decoded byte is negative. Low when the current
running disparity of the 8B/10B decoded byte is positive.
rx_syncstatus[7:0]
Output Synchronization indication. RX synchronization is
indicated on the
rx_syncstatus
port of each channel.
The
rx_syncstatus
signal is 2 bits wide per channel for a
total of 8 bits per XAUI link.
rx_phase_comp_fifo_
error[3:0]
Output Indicates a RX phase comp FIFO overflow or underrun
condition.
tx_phase_comp_fifo_
error[3:0]
Output Indicates a TX phase compensation FIFO overflow or
underrun condition.
rx_rlv[3:0]
Output Asserted if the number of continuous 1s and 0s exceeds
the number that was set in the run-length option. The
rx_rlv
signal is asynchronous to the RX datapath and is
asserted for a minimum of 2 recovered clock cycles.
rx_recovered_clk
Output This is the RX clock which is recovered from the received
data stream.
XAUI PHY Register Interface and Register Descriptions
This section describes the register interface and descriptions for the IP core.
The Avalon-MM PHY management interface provides access to the XAUI PHY IP Core PCS, PMA, and
transceiver reconfiguration registers.
6-18 XAUI PHY Register Interface and Register Descriptions
UG-01080
2015.01.19
Altera Corporation XAUI PHY IP Core
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