Altera Transceiver PHY IP Core - Manual (Page 194)

• PHY Interface for the PCI Express Architecture PCI Express 3.0
PHY for PCIe (PIPE) Interfaces
This section describes interfaces of the PHY IP Core for PCI Express (PIPE).
The following figure illustrates the top-level pinout of the PHY IP Core for PCI Express PHY. The port
descriptions use the following variables to represent parameters:
• <n>—The number of lanes
• <d>—The total deserialization factor from the input pin to the PHY MAC interface.
• <s>—The symbols size.
• <r>—The width of the reconfiguration interface; is automatically calculated based on the selected
configuration.
Figure 8-3: Top-Level Signals of the PHY IP Core for PCI Express
PHY IP Core for PCI Express Top-Level Signals
tx_serial_data[ -1:0]
rx_serial_data[ -1:0]
pll_ref_clk
fixedclk
pipe_pclk
rx_ready
rx_ready
pll_locked
rx_is_lockedtodata[ -1:0]
rx_is_lockedtoref[ -1:0]
rx_syncstatus[ / -1:0]
rx_signaldetect[ / -1:0]
High Speed
Serial I/O
Avalon-MM PHY
Management
Interface
to Embedded
Controller
PIPE Input
from
MAC PHY
PIPE Output
to MAC PHY
Clocks
Status
pipe_txdata[31:0],[15:0],[7:0]
pipe_txdatak[3:0],[1:0],[0]
pipe_txcompliance[ -1:0]
pipe_tx_data_valid[ -1:0]
tx_blk_start[3:0]
tx_sync_hdr[1:0]
pipe_txdetectrx_loopback[ -1:0]
pipe_txelecidle[ -1:0]
pipe_powerdown[2 -1:0]
pipe_g3_txdeemph[17:0]
pipe_txmargin[2-1:0]
pipe_txswing
pipe_rxpolarity[ -1:0]
pipe_rate[1:0]
rx_eidleinfersel[2-1:0]
pipe_rxpresethint[2:0]
pipe_rxdata[31:0],[15:0],[7:0]
pipe_rxdatak[3:0],[1:0],[0]
rx_blk_start[3:0]
rx_syc_hdr[1:0]
pipe_rx_data_valid[ -1:0]
pipe_rxvalid[ -1:0]
pipe_rxelecidle[ -1:0]
rxstatus[3 -1:0]
pipe_phystatus[ -1:0]
phy_mgmt_clk
phy_mgmt_clk_reset
phy_mgmt_address[8:0]
phy_mgmt_writedata[31:0]
phy_mgmt_readdata[31:0]
phy_mgmt_write
phy_mgmt_read
phy_mgmt_waitrequest
reconfig_to_xcvr[( 70 )-1:0]
reconfig_from_xcvr[( 46)-1:0]
Dynamic
Reconfiguation
Note: The block diagram shown in the GUI labels the external pins with the interface type and places the
interface name inside the box. The interface type and name are used in the _hw.tcl file. If you turn
on Show signals, the block diagram displays all top-level signal names.
8-6 PHY for PCIe (PIPE) Interfaces
UG-01080
2015.01.19
Altera Corporation PHY IP Core for PCI Express (PIPE)
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