Altera Transceiver PHY IP Core - Manual (Page 173)

Click on the appropriate link to specify the analog options for your device:
Related Information
• Analog Settings for Arria V GZ Devices on page 19-11
• Analog Settings for Stratix V Devices on page 19-34
Interlaken PHY Interfaces
This section describes the Interlaken PHY interfaces.
The following figure illustrates the top-level signals of the Interlaken PHY IP Core; <n> is the channel
number so that the width of
tx_data
in 4-lane instantiation is [263:0].
Figure 7-2: Top-Level Interlaken PHY Signals
tx_parallel_data [65:0]
tx_ready
tx_datain_bp
tx_clkout
tx_user_clkout
pll_locked
tx_sync_done
rx_parallel_data [71:0]
rx_ready
rx_clkout
rx_fifo_clr
rx_dataout_bp
phy_mgmt_clk
phy_mgmt_clk_reset
phy_mgmt_address[8:0]
phy_mgmt_writedata[31:0]
phy_mgmt_readdata[31:0]
phy_mgmt_write
phy_mgmt_read
phy_mgmt_waitrequest
pll_ref_clk
Interlaken Top-Level Signals
tx_serial_data
rx_serial_data
Avalon-ST
TX to/ from
MAC
High Speed
Serial I/O
PLL
Avalon-MM PHY
Management
Interface
Avalon-ST
RX from/to
MAC Dynamic
Reconfiguation
tx_coreclkin
rx_coreclkin
reconfig_to_xcvr[( 70-1):0]
reconfig_from_xcvr[( 46-1):0]
FIFO Clock
Input
(Optional)
Note: The block diagram shown in the GUI labels the external pins with the interface type and places the
interface name inside the box. The interface type and name are used to define interfaces in the
_hw.tcl. writing.
For more information about _hw.tcl, files refer to the Component Interface Tcl Reference chapter in
volume 1 of the Quartus II Handbook.
Related Information
Component Interface Tcl Reference
7-6 Interlaken PHY Interfaces
UG-01080
2015.01.19
Altera Corporation Interlaken PHY IP Core
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