Altera Transceiver PHY IP Core User Manual
Page 87
Signal Name
Direction
Description
pcs_mode_rc[5:0]
Output
Specifies the PCS mode for reconfig using 1-hot
encoding. The following modes are defined:
• 6'b000001: Auto-Negotiation mode
• 6'b000010: Link Training mode
• 6'b000100: 10GBASE-KR data mode
• 6'b001000: GigE data mode
• 6'b010000: Reserved
• 6'b100000:10G data mode with FEC
dfe_start_rc
Output
When asserted, starts the RX DFE equalization of
the PMA.
dfe_mode[1:0]
Output
Specifies the DFE operation mode. Valid at the
rising edge of the
def_start_rc
signal and held
until the falling edge of the
rc_busy
signal. The
following encodings are defined:
• 2'b00: Disable DFE
• 2'b01: DFE triggered mode
• 2'b10: Reserved
•
def_start_rc
d'b11: Reserved
ctle_start_rc
Output
When asserted, starts continuous time-linear
equalization (CTLE) reconfiguration.
ctle_mode[1:0]
Output
Specifies CTLE mode. These signals are valid at the
rising edge of the
ctle_start_rc
signal and held
until the falling edge of the
rc_busy
signal. The
following encodings are defined:
• 2'b00:
ctle_rc[3:0]
drives the value of CTLE
set during link training
• 2'b01: Reserved
• 2b'10: Reserved
• 2'b11: Reserved
ctle_rc[3:0]
Output
RX CTLE value. This signal is valid at the rising
edge of the
ctle_start_rc
signal and held until the
falling edge of the
rc_busy
signal. The valid range
of values is 4'b0000-4'b1111.
mode_1g_10gbar
Input
This signal indicates the requested mode for the
channel. A 1 indicates 1G mode and a 0 indicates
10G mode. This signal is only used when the
sequencer which performs automatic speed
detection is disabled.
en_lcl_rxeq
Output
This signal is not used. You can leave this
unconnected.
UG-01080
2015.01.19
Dynamic Reconfiguration Interface Signals
4-31
Backplane Ethernet 10GBASE-KR PHY IP Core with Early Access FEC Option
Altera Corporation