10gbase-kr phy control and status interfaces, 10gbase-kr phy control and status interfaces -25 – Altera Transceiver PHY IP Core User Manual
Page 81
10GBASE-KR PHY Control and Status Interfaces
The 10GBASE-KR XGMII and GMII interface signals drive data to and from PHY.
Table 4-14: Control and Status Signals
Signal Name
Direction
Description
rx_block_lock
Output
Asserted to indicate that the block synchronizer has
established synchronization.
rx_hi_ber
Output
Asserted by the BER monitor block to indicate a
Sync Header high bit error rate greater than 10
-4
.
pll_locked
Output
When asserted, indicates the TX PLL is locked.
rx_is_lockedtodata
Output
When asserted, indicates the RX channel is locked
to input data.
tx_cal_busy
Output
When asserted, indicates that the initial TX calibra‐
tion is in progress. It is also asserted if reconfigura‐
tion controller is reset. It will not be asserted if you
manually re-trigger the calibration IP. You must
hold the channel in reset until calibration
completes.
rx_cal_busy
Output
When asserted, indicates that the initial RX calibra‐
tion is in progress. It is also asserted if reconfigura‐
tion controller is reset. It will not be asserted if you
manually re-trigger the calibration IP.
calc_clk_1g
Input
An independent clock to calculate the latency of the
SGMII TX and RX FIFOs. It is only required for
when you enable 1588 in 1G mode.
The
calc_clk_1g
should have a frequency that is
not equivalent to 8 ns (125MHz). The accuracy of
the PCS latency measurement is limited by the
greatest common denominator (GCD) of the RX
and TX clock periods (8 ns) and
calc_clk_1g
. The
GCD is 1 ns, if no other higher common factor
exists. When the GCD is 1, the accuracy of the
measurement is 1 ns. If the period relationship has
too small a phase, the phase measurement requires
more time than is available. Theoretically, 8.001 ns
would provide 1 ps of accuracy. But this phase
measurement period requires 1000 cycles to
converge which is beyond the averaging capability
of the design. The GCD of the clock periods should
be no less than 1/64 ns (15ps).
To achieve high accuracy for all speed modes, the
recommended frequency for
calc_clk_1g
is 80
MHz. In addition, the 80 MHz clock should have
same parts per million (ppm) as the 125 MHz
pll_
UG-01080
2015.01.19
10GBASE-KR PHY Control and Status Interfaces
4-25
Backplane Ethernet 10GBASE-KR PHY IP Core with Early Access FEC Option
Altera Corporation