Altera Transceiver PHY IP Core - Manual (Page 198)

Signal Name Direction Description
rx_eidleinfersel[3-1:0]
Input
When asserted high, the electrical idle state is
inferred instead of being identified using analog
circuitry to detect a device at the other end of the
link. The following encodings are defined:
• 3'b0xx: Electrical Idle Inference not required in
current LTSSM state
• 3'b100: Absence of COM/SKP OS in 128 ms
window for Gen1 or Gen2
• 3'b101: Absence of TS1/TS2 OS in 1280 UI
interval for Gen1 or Gen2
• 3'b110: Absence of Electrical Idle Exit in 2000
UI interval for Gen1 and 16000 UI interval for
Gen2
• 3'b111: Absence of Electrical Idle exit in 128 ms
window for Gen1
pipe_rxpresethint[2:0]
Input Provides the RX preset hint for the receiver. Only
used for the Gen3 data rate.
Table 8-4: Preset Mappings to TX De-Emphasis
Preset C
+1
C
0
C
-1
1 001001 011010 000000
2 000110 011101 000000
3 000111 011100 000000
4 000101 011110 000000
5 000000 100011 000000
6 000000 011111 000100
7 000000 011110 000101
8 000111 011000 000100
9 000101 011010 000100
10 000000 011101 000110
11 001011 011000 000000
Related Information
• Avalon Interface Specifications
• Intel PHY Interface for PCI Express (PIPE) Architecture
• PCI Express Base Specification, Rev. 3.
8-10 PHY for PCIe (PIPE) Input Data from the PHY MAC
UG-01080
2015.01.19
Altera Corporation PHY IP Core for PCI Express (PIPE)
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