Altera Transceiver PHY IP Core User Manual
Page 258
Name
Value
Description
Number of TX PLLs
1–4
Specifies the number of TX PLLs that can be
used to dynamically reconfigure channels to
run at multiple data rates. If your design
does not require transceiver TX PLL
dynamic reconfiguration, set this value to 1.
The number of actual physical PLLs that are
implemented depends on the selected clock
network. Each channel can dynamically
select between n PLLs, where n is the
number of PLLs specified for this parameter.
You must disable the embedded reset
controller and design your own controlled
reset controller or the use the highly
configurable reset core described in
Transceiver PHY Reset Controller IP Core if
you intend to use more than 1 TX PLL for a
Low Latency PHY IP instance.
Note: For more details, refer to the
Transceiver Clocking chapter in
the device handbook for the
device family you are using.
Number of reference clocks
1–5
Specifies the number of input reference
clocks. More than one reference clock may
be required if your design reconfigures
channels to run at multiple frequencies.
Main TX PLL logical index
0–3
Specifies the index for the TX PLL that
should be instantiated at startup. Logical
index 0 corresponds to TX PLL0, and so on.
CDR PLL input clock source
0–3
Specifies the index for the TX PLL input
clock that should be instantiated at startup.
Logical index 0 corresponds to input clock 0
and so on.
TX PLL (0–3)
(Refer to
Low Latency PHY General Options
for a detailed explanation of these parameters.)
PLL Type
CMU
ATX
Specifies the PLL type.
Base data rate
1 × Data rate
2 × Data rate
4 × Data rate
8 × Data rate
Specifies Base data rate.
UG-01080
2015.01.19
PLL Reconfiguration Parameters
10-11
Low Latency PHY IP Core
Altera Corporation