Altera Transceiver PHY IP Core - Manual (Page 71)

• Channel number—specifies the requested channel
• Mode—specifies 1G or 10G data modes or AN or LT modes for the corresponding channel
2. Select a channel for reconfiguration and send an ack/busy signal to the requestor. The requestor
should deassert its request signal when the ack/busy is received.
3. Pass the selected channel and rate information or PMA reconfiguration information for LT to the state
machine for processing.
4. Wait for a done signal from the state machine indicating that the reconfiguration process is complete
and it is ready to service another request.
Related Information
10GBASE-KR Dynamic Reconfiguration from 1G to 10GbE
10GBASE-KR PHY State Machine Logic Requirements
The state machine should implement the following logic. You can modify this logic based on your system
requirements:
1. Wait for
reconfig_busy
from the Transceiver Reconfiguration Controller to be deasserted and the
tx_ready
and
rx_ready
signals from the Transceiver PHY Reset Controller to be asserted. These
conditions indicate that the system is ready to service a reconfiguration request.
2. Set the appropriate channel for reconfiguration.
3. Initiate the MIF streaming process. The state machine should also select the appropriate MIF (stored
in the ROMs) to stream based on the requested mode.
4. Wait for the
reconfig_busy
signal from the Transceiver Reconfiguration Controller to assert and
then deassert indicating the reconfiguration process is complete.
5. Toggle the digital resets for the reconfigured channel and wait for the link to be ready.
6. Deassert the
ack/busy
signal for the selected channel. Deassertion of
ack/busy
indicates to the arbiter
that the reconfiguration process is complete and the system is ready to service another request.
Related Information
• Transceiver PHY Reset Controller IP Core on page 17-1
• Transceiver Reconfiguration Controller IP Core Overview on page 16-1
Forward Error Correction (Clause 74)
The optional Forward Error Correction (FEC) function is defined in Clause 74 of IEEE 802.3ap-2007. It
provides an error detection and correction mechanism allowing noisy channels to achieve the Ethernet-
mandated Bit Error Rate (BER) of 10 -12 .
The following figure illustrates the interface between the FEC, PCS and PMA modules as defined in
IEEE802.3ap-2007.
UG-01080
2015.01.19
10GBASE-KR PHY State Machine Logic Requirements 4-15
Backplane Ethernet 10GBASE-KR PHY IP Core with Early Access FEC Option Altera Corporation
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