Byte order parameters, Byte order parameters -11 – Altera Transceiver PHY IP Core User Manual
Page 224
Table 9-8: 8B/10B Options
Name
Value
Description
Enable 8B/10B decoder/encoder
On/Off
Enable this option if your application
requires 8B/10B encoding and
decoding. This option on adds the
tx_datak
,
rx_datak
, and
rx_runningdisp
signals to your
transceiver.
Enable manual disparity control
On/Off
When enabled, you can use the
tx_
forcedisp
signal to control the
disparity of the 8B/10B encoder.
Turning this option on adds the
tx_
forcedisp
and
tx_dispval
signals
to your transceiver.
Create optional 8B/10B status port
On/Off
Enable this option to include the 8B/
10B
rx_errdetect
and
rx_disperr
error signals at the top level of the
Custom PHY IP Core.
Byte Order Parameters
The byte ordering block is available when the PCS width is doubled at the byte deserializer. Byte ordering
identifies the first byte of a packet by determining whether the programmed start-of-packet (SOP) pattern
is present; it inserts enough pad characters in the data stream to force the SOP to the lowest order byte
lane.
Note: You cannot enable Rate Match FIFO when your application requires byte ordering. Because the
rate match function inserts and deletes idle characters, it may shift the SOP to a different byte lane.
UG-01080
2015.01.19
Byte Order Parameters
9-11
Custom PHY IP Core
Altera Corporation