Altera Transceiver PHY IP Core - Manual (Page 236)

Signal Name Direction Description
rx_clkout[< n >-1:0]
Output This is the clock for the RX parallel data source
interface.
rx_datak[< n >(/)-1:0]
Output Data and control indicator for the source data.
When 0, indicates that
rx_parallel_data
is data,
when 1, indicates that
rx_parallel_data
is
control.
rx_runningdisp[< n >(/)-
1:0]
Output This status signal indicates the disparity of the
incoming data.
rx_enabyteord[< n >-1:0]
Input This signal is created if you turn On the Enable
byte ordering block control option on the Byte
Order tab. A byte ordering operation occurs
whenever
rx_enabyteord
is asserted. To perform
multiple byte ordering operations, deassert and
reassert
rx_enabyteord
.
Table 9-15: Location of Valid Data Words for rx_parallel_data for Various FPGA Fabric to PCS
Parameterizations
The following table shows the valid 11-bit data words with and without the byte deserializer for single- and
double-word FPGA fabric to PCS interface widths. The byte deserializer allows the PCS to operate at twice the
data width of the PMA . This feature allows the PCS to run at a lower frequency and accommodates a wider range
of FPGA interface widths.
Configuration Location of rx_parallel_data
Single word data bus, byte deserializer disabled [15:0] (word 0)
Single word data bus, byte serializer enabled [47:32], [15:0] (words 0 and 2)
Double word data bus, byte serializer disabled [31:0] (words 0 and 1)
Double word data bus, byte serializer enabled [63:0] (words 0-3)
Table 9-16: Serial Interface and Status Signals
Signal Name Direction Signal Name
rx_serial_data[< n >-1:0]
Input Receiver differential serial input data.
tx_serial_data[< n >-1:0]
Output Transmitter differential serial output data.
Clock Interface
The input reference clock,
pll_ref_clk
, drives a PLL inside the PHY-layer block, and a PLL output clock,
rx_clkout
is used for all data, command, and status inputs and outputs.
UG-01080
2015.01.19
Clock Interface 9-23
Custom PHY IP Core Altera Corporation
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