10g pcs parameters for stratix v native phy, 10g pcs parameters for stratix v native phy -29 – Altera Transceiver PHY IP Core User Manual
Page 327
10G PCS Parameters for Stratix V Native PHY
This section shows the complete datapath and clocking for the 10G PCS and defines parameters available
in the GUI to enable or disable the individual blocks in the 10G PCS.
Figure 12-4: The 10G PCS datapath
FPGA
Fabric
Transmitter 10G PCS
Receiver 10G PCS
Transmitter PMA
Receiver PMA
TX FIFO
RX FIFO
Frame G
ener
at
or
CRC32 Gener
at
or
CRC32 Check
er
64B/66B E
nc
oder
and T
X SM
64B/66B D
ec
oder
and R
X SM
Scr
ambler
Descr
ambler
Disparit
y C
heck
er
Block
Synchr
oniz
er
Frame S
ync
Disparit
y
Gener
at
or
TX
Gear B
ox
RX
Gear B
ox
Serializ
er
Deserializ
er
CDR
tx_serial_data
rx_serial_data
rx_c
or
eclk
in
tx_c
or
eclk
in
Input Reference Clock
(From Dedicated Input Reference Clock Pin)
BER
Monitor
Clock Divider
Parallel and Serial Clocks
Serial Clock
Central/ Local Clock Divider
Parallel Clock
Serial Clock
Parallel and Serial Clocks
CMU PLL /
ATX PLL /
fPLL
tx_clkout
rx_clkout
PRBS
Generator
(1)
PRP
Generator
PRP
Verifier
PRBS
Verifier
Note:
1. The PRBS pattern generator can dynamically invert the data pattern that leaves the PCS block.
UG-01080
2015.01.19
10G PCS Parameters for Stratix V Native PHY
12-29
Stratix V Transceiver Native PHY IP Core
Altera Corporation