Altera Transceiver PHY IP Core User Manual
Page 549
DCD runs automatically at power up. After power up, you can rerun DCD by writing to the DCD control
register. Altera recommends that you run DCD calibration for Arria V and Cyclone V devices if the data
rate is greater than 4.9152 Gbps.
Note: All undefined register bits are reserved.
Table 16-21: DCD Registers
Reconfig Addr
Bits
R/W
Register Name
Description
7’h48
[9:0] RW
logical channel number
The logical channel number. Must be
specified when performing dynamic
updates. The Transceiver Reconfiguration
Controller maps the logical address to the
physical address.
7’h4B
[6:0] RW
dcd offset
Specifies the offset of the DCD setting to
be reconfigured.
#nik1398984276755/
table_
A420703A5C8042E3872CA7C66487930E
describes the valid offset values.
7’h4C
[6:0] RW
dcd_data
Reconfiguration data for the PMA analog
settings.
Note: All undefined register bits are reserved.
Table 16-22: DCD Offsets and Values
Offset
Bits
R/W
Register Name
Description
0x0
[5:0]
RW
dcd_control
Writing 1'b1 to this bit to manually
triggers DCD calibration.
Transceiver Reconfiguration Controller Channel and PLL Reconfiguration
You can use channel and PLL reconfiguration to dynamically reconfigure the channel and PLL settings in
a transceiver PHY IP core.
Among the settings that you can change dynamically are the data rate and interface width. Refer to Device
Support for Dynamic Reconfiguration for specific information about reconfiguration in Arria V, Cyclone
V, and Stratix V devices.
The Transceiver Reconfiguration Controller’s Streamer Module implements channel and PLL reconfigu‐
ration. Refer to the Streamer Module Registers for more information about this module.
Note: Channel and PLL reconfiguration are available for the Custom, Low Latency, Deterministic
Latency PHY IP Cores, the Arria V Native PHY, the Arria V GZ Native PHY, the Cyclone V Native
PHY, and the Stratix V Native PHY.
16-32
Transceiver Reconfiguration Controller Channel and PLL Reconfiguration
UG-01080
2015.01.19
Altera Corporation
Transceiver Reconfiguration Controller IP Core Overview