Altera Parallel Flash Loader IP User Manual
Parallel flash loader ip core user guide, Features, Installing and licensing ip cores
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Parallel Flash Loader IP Core User Guide
2015.01.23
UG-01082
This document describes how to instantiate the Parallel Flash Loader (PFL) IP core in your design,
programming flash memory, and configuring your FPGA from the flash memory.
FPGAs’ increasing density requires larger configuration storage. If your system contains a flash memory
device, you can use your flash memory as the FPGA configuration storage as well. You can use the PFL IP
core in Altera
®
MAX
®
Series (MAX II, MAX V and MAX 10 devices) or all other FPGAs to program
flash memory devices efficiently through the JTAG interface and to control configuration from the flash
memory device to the Altera FPGA.
Features
Use the PFL IP core to:
• Program Common Flash Interface (CFI) flash, quad Serial Peripheral Interface (SPI) flash, or NAND
flash memory devices with the device JTAG interface.
• Control Altera FPGA configuration from a CFI flash, quad SPI flash, or NAND flash memory device
for Arria series, Cyclone series, and Stratix series FPGA devices.
Installing and Licensing IP Cores
The Altera IP Library provides many useful IP core functions for production use without purchasing an
additional license. You can evaluate any Altera
®
IP core in simulation and compilation in the Quartus
®
II
software using the OpenCore
®
evaluation feature. Some Altera IP cores, such as MegaCore
®
functions,
require that you purchase a separate license for production use. You can use the OpenCore Plus feature to
evaluate IP that requires purchase of an additional license until you are satisfied with the functionality and
performance. After you purchase a license, visit the Self Service Licensing Center to obtain a license
number for any Altera product.
Figure 1: IP Core Installation Path
acds
quartus - Contains the Quartus II software
ip - Contains the Altera IP Library and third-party IP cores
altera - Contains the Altera IP Library source code
©
2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are
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trademarks or service marks are the property of their respective holders as described at
www.altera.com/common/legal.html
. Altera warrants performance
of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,
product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.
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101 Innovation Drive, San Jose, CA 95134
Document Outline
- Parallel Flash Loader IP Core User Guide
- Features
- Installing and Licensing IP Cores
- Device Support
- IP Catalog and Parameter Editor
- Using the Parameter Editor
- Functional Description
- Using the PFL IP Core
- Customizing and Generating IP Cores
- Converting .sof Files to a .pof
- Constraining PFL Timing
- Simulating PFL Design
- Programming Altera CPLDs and Flash Memory Devices
- Defining New CFI Flash Device
- Programming Multiple Flash Memory Devices
- Creating Jam Files for Altera CPLDs and Flash Memory Device Programming
- PFL IP Core In Embedded Systems
- Third-party Programmer Support
- Parameters
- Signals
- Specifications
- Document Revision History