Altera Transceiver PHY IP Core - Manual (Page 567)

//Generator selection and setup
read_32 0x3A //Read the control and status register
//busy bit[8] until it is clear
write_32 0x38 0x0 //write logical channel to 0x38
write_32 0x3A 0x4 //set the MIF mode 1 to address 0x3A
write_32 0x3B 0x135 //write the pattern type offset
write_32 0x3A 0x6//write the control and status register
//with a value of 0x6 to address 0x3A to initiate a read
read_32 0x3C //Read the value at address 0x3C
RMW {3’b1-01, {read_32 0x3C}} //Perform a read-modify-write
//with the generator or bits and the value read from above
write_32 0x3C 0x //Write the new value
//from above to the data register at address 0x3C
write_32 0x3A 0x5 //Write the control and status register with
//a value of 0x5 to address 0x3A
//Assert the channel resets
Disabling the Standard PCS PRBS Generator and Verifier Using Streamer-Based
Reconfiguration
To disable the PRBS generator or verifier, restore the original values of all registers written to enable the
PRBS generator or verifier. Restoring the original values requires you to save them while performing the
read-modify-write operations.
Understanding Logical Channel Numbering
This discussion of channel numbering, uses the following definitions:
• Reconfiguration interface—A bundle of signals that connect the Transceiver Reconfiguration
Controller to a transceiver PHY data channel or TX PLL.
• Logical channels—An abstract representation of a channel or TX PLL that does not include physical
location information.
• Bonded channel—A channel that shares a clock source with at least one other channel.
• Physical channel—The physical channel associated with a logical channel.
The following figure illustrates the connections between the Transceiver Reconfiguration Controller and a
transceiver bank after running the Quartus II Fitter.
Figure 16-8: Post-Fit Connectivity
Transceiver
Reconfiguration
Controller
Transceiver Bank
3 Channels
3 Channels
Channel 2
Channel 1
Channel 0
Channel 3
Channel 5
Channel 4
S M
to Embedded
Processor
Reconfig to
and from
Transceiver
Stratix V GX, GS, or GT Device
S
S
16-50 Disabling the Standard PCS PRBS Generator and Verifier Using Streamer-Based
Reconfiguration
UG-01080
2015.01.19
Altera Corporation Transceiver Reconfiguration Controller IP Core Overview
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