Altera Transceiver PHY IP Core User Manual
Page 681
Date
Document
Version
Changes Made
February 2013
1.9
• Reformatted.
• Corrected definition of
rx_data_ready
. This signal is used and
indicates that the PCS is ready to receive data.
• Removed description of PMA
reset_ch_bitmask
at 0x41 and
reset_control at 0x42 which are not available.
• Removed definitions of
trn_in_trigger
and
trn_out_
trigger
buses which are not used.
XAUI PHY
February 2013
1.9
• Reformatted.
Interlaken PHY
February 2013
1.9
• Reformatted.
• Improved definitions of
rx_parallel_data
,
rx_
dataout_bp
and typo in definition of
tx_user_clkout
.
PHY IP Core for PCI Express (PIPE)
February 2013
1.9
• Reformatted.
Custom PHY
February 2013
1.9
• Reformatted.
Low Latency PHY
February 2013
1.9
• Reformatted.
Deterministic Latency PHY
February 2013
1.9
• Reformatted.
• Corrected headings in Table 11-4. The TX PMA Latency in UI
and RX PMA Latency in UI were previously reversed.
• In Table 11-3, added explanation of a latency uncertainty of 0.5
cycles when the byte serializer/deserializer is turned on. The
location of the alignment pattern which can be in the upper or
lower symbol.
Stratix V Native PHY
February 2013
1.9
• Reformatted.
• Added missing descriptions of Interlaken parameters to 10G RX
FIFO section.
• Improved definition of
pll_powerdown
signal.
Arria V Native PHY
UG-01080
2015.01.19
Revision History for Previous Releases of the Transceiver PHY IP Core
21-21
Additional Information for the Transceiver PHY IP Core
Altera Corporation