Altera Transceiver PHY IP Core - Manual (Page 471)

Name Dir Synchro‐
nous to tx_
10g_
coreclkin/
rx_10g_
coreclkin
Description
tx_10g_coreclkin
[-1:0] Input —
TX parallel clock input that drive the write side of
the TX FIFO.
rx_10g_coreclkin
[-1:0]
Input — RX parallel clock input that drives the read side of
the RX FIFO.
tx_10g_clkout
[-1:0]
Output — TX parallel clock output for the TX PCS.
rx_10g_clkout
[-1:0]
Output — RX parallel clock output which is recovered from
the RX data stream.
rx_10g_clk33out
[-1:0]
Output — This clock is driven by the RX deserializer. Its
frequency is RX CDR PLL clock frequency divided
by 33 or equivalently the RX PMA data rate
divided by 66. It is typically used for ethernet
applications that use 66b/64b decoding.
TX FIFO
tx_10g_control
[9-1:0] Input Yes
TX control signals for the Interlaken, 10GBASE-R,
and Basic protocols. Synchronous to tx_10g_
coreclk_in. The following signals are defined:
Interlaken mode:
• [8]: Active-high synchronous error insertion
control bit
• [7:3]: Not Used
14-60 10G PCS Interface
UG-01080
2015.01.19
Altera Corporation Arria V GZ Transceiver Native PHY IP Core
Send Feedback