Altera Transceiver PHY IP Core User Manual
Page 521
The Transceiver Reconfiguration Controller provides two modes to dynamically reconfigure transceiver
settings:
• Register Based—In this access mode you can directly reconfigure a transceiver PHY IP core using the
Transceiver Reconfiguration Controller’s reconfiguration management interface. You initiate reconfi‐
guration using a series of Avalon-MM reads and writes to the appropriate registers of the Transceiver
Reconfiguration Controller. The Transceiver Reconfiguration Controller translates the device
independent commands received on the reconfiguration management interface to device dependent
commands on the transceiver reconfiguration interface. For more information, refer to Changing
Transceiver Settings Using Register-Based Reconfiguration.
For more information about Avalon-MM interfaces including timing diagrams, refer to the Avalon
Interface Specifications.
• Streamer Based —This access mode allows you to either stream a MIF that contains the reconfigura‐
tion data or perform direct writes to perform reconfiguration. The streaming mode uses a memory
initialization file (.mif) to stream an update to the transceiver PHY IP core. The .mif file can contain
changes for many settings. For example, a single .mif file might contain changes to the PCS datapath
settings, clock settings, and PLL parameters. You specify the .mif using write commands on the
Avalon-MM PHY management interface. After the streaming operation is specified, the update
proceeds in a single step. For more information, refer to Changing Transceiver Settings Using Streamer-
Based Reconfiguration. In the direct write mode, you perform Avalon-MM reads and writes to initiate
a reconfiguration of the PHY IP. For more information, refer to Direct Write Reconfiguration.
The following table shows the features that you can reconfigure or control using register-based and MIF-
based access modes for Stratix V devices.
Table 16-2: Reconfiguration Feature Access Modes
Feature
Register-Based
Streamer-Based
PMA settings, including V
OD
, pre-emphasis, RX equalization
DC gain, RX equalization control
Yes
Yes
Pre-CDR and post-CDR loopback modes
Yes
—
DFE post taps and polarity
Yes
—
AEQ mode
Yes
—
Eye Monitor
Yes
—
ATX Tuning
Yes
Yes
Reference clock
Yes
Yes
TX PLL clock switching
—
Yes
Channel interface
—
Yes
Related Information
•
Changing Transceiver Settings Using Register-Based Reconfiguration
•
Changing Transceiver Settings Using Streamer-Based Reconfiguration
on page 16-43
•
on page 16-44
•
16-4
Transceiver Reconfiguration Controller System Overview
UG-01080
2015.01.19
Altera Corporation
Transceiver Reconfiguration Controller IP Core Overview