Altera Transceiver PHY IP Core - Manual (Page 553)

Offset Bits R/W Register Name Description
0x2
[4] RO
MIF or Channel mismatch When asserted, indicates the MIF type
specified is incorrect. For example, the
logical channel is duplex, but the MIF type
specifies an RX only channel. The
following 5 MIF types are defined:
• Duplex
• TX PLL (CMU)
• RX only channel
• TX only channel
• TX PLL (ATX)
[2] RO
PLL reconfiguration IP error
When asserted, indicates that an error
occurred changing a refclk or clock
generation block setting.
[1] RO
MIF opcode error
When asserted, indicates that an undefined
opcode ID was specified in the .mif file, or
the first entry in the .mif file was not a
start of MIF opcode.
[0] RO
Invalid register access
When asserted, indicates that the offset
register address specified is out of range.
Mode 0 Streaming a MIF for Reconfiguration
In mode 0, you can stream the contents of a MIF containing the reconfiguration data to the transceiver
PHY IP core instance.
You specify this mode by writing a value of 2'b00 into bits 2 and 3 of the control and status register, as
indicated in Streamer Module Registers. Mode 0 simplifies the reconfiguration process because all reconfi‐
guration data is stored in the MIF, which is streamed to the transceiver PHY IP in a single step.
The MIF can change PLL settings, reference clock inputs, or the TX PLL selection. After the MIF
streaming update is complete, all transceiver PHY IP core settings reflect the value specified by the MIF.
Refer to Streamer-Based Reconfiguration for an example of a MIF update.
Mode 1 Avalon-MM Direct Writes for Reconfiguration
This section describes mode 1 Avalon-MM direct writes for reconfiguration.
You specify this mode by writing a value of 2'b01 into bits 2 and 3 of the control and status register, as
indicated in Streamer Module Registers. In this mode, you can write directly to transceiver PHY IP core
registers to perform reconfiguration. Refer to “Direct Write Reconfiguration” for an example of an update
using mode 1. In mode 1, you can selectively reconfigure portions of the transceiver PHY IP core. Unlike
mode 0, mode 1 allows you to write only the data required for a reconfiguration.
16-36 Mode 0 Streaming a MIF for Reconfiguration
UG-01080
2015.01.19
Altera Corporation Transceiver Reconfiguration Controller IP Core Overview
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