Altera Transceiver PHY IP Core - Manual (Page 386)

Note: For more information about the Standard PCS, refer to the PCS Architecture section in the
Transceiver Architecture in Arria V Devices.
The following table describes the general and datapath options for the Standard PCS.
Table 13-10: General and Datapath Parameters
Parameter Range Description
Standard PCS protocol
mode
basic cpri gige
Specifies the protocol that you intend to implement with
the Native PHY. The protocol mode selected guides the
MegaWizard in identifying legal settings for the Standard
PCS datapath.
Use the following guidelines to select a protocol mode:
• basic–select this mode for when none of the other
options are appropriate. You should also select this
mode to enable diagnostics, such as loopback.
• cpri–select this mode if you intend to implement
CPRI or another protocol that requires deterministic
latency. Altera recommends that you select the
appropriate CPRI preset for the CPRI protocol.
• gige–select this mode if you intend to implement
either the 1.25 Gbps or 2.5 Gbps Ethernet protocol.
Altera recommends that you select the appropriate
preset for the Ethernet protocol.
Standard PCS/PMA
interface width
8, 10,16, 20 Specifies the width of the datapath that connects the
FPGA fabric to the PMA. The transceiver interface width
depends upon whether you enable 8B/10B. To simplify
connectivity between the FPGA fabric and PMA, the bus
bits used are not contiguous for 16 and 32bit buses. Refer
to Active Bits for Each Fabric Interface Width for the bits
used.
FPGA fabric/Standard
TX PCS interface width
8, 10,16, 20, 32, 40 Shows the FPGA fabric to TX PCS interface width which
is calculated from the Standard PCS/PMA interface
width .
FPGA fabric/Standard
RX PCS interface width
8, 10,16, 20, 32, 40 Shows the FPGA fabric to RX PCS interface width which
is calculated from the Standard PCS/PMA interface
width .
Enable ‘Standard PCS’
low latency mode
On/Off When you turn this option On, all PCS functions are
disabled except for the phase compensation FIFO, byte
serializer and byte deserializer. This option creates the
lowest latency Native PHY that allows dynamic
reconfigure between multiple PCS datapaths.
UG-01080
2015.01.19
Standard PCS Parameters 13-11
Arria V Transceiver Native PHY IP Core Altera Corporation
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