Altera Transceiver PHY IP Core User Manual
Page 456
Offset
Bits
R/W
Name
Description
0x15E
[14]
R/W
RX PRBS 7 Enable
Enables the PRBS-7 polynomial in the
receiver.
[13]
R/W
RX PRBS 23 Enable
Enables the PRBS-23 polynomial in the
receiver.
[12]
R/W
RX PRBS 9 Enable
Enables the PRBS-9 polynomial in the
receiver.
[11]
R/W
RX PRBS 31 Enable
Enables the PRBS-31 polynomial in the
receiver.
[10]
R/W
RX Test Enable
Enables the PRBS pattern verifier in the
receiver.
0x164
[10]
R/W
RX PRBS Clock Enable
Enables the receiver PRBS Clock.
0x169
[0]
R/W
RX Test Pattern
Select
Selects between a square wave or
pseudo-random pattern. The following
encodings are defined:
• 1’b1: Square wave
• 1’b0: Pseudo-random pattern or
PRBS
PRBS Pattern Generator
To enable the PRBS pattern generator, write 1'b1 to the
RX PRBS Clock Enable
and
TX PRBS Clock
Enable
bits.
The following table shows the available PRBS patterns:
Table 14-37: 10G PCS PRBS Patterns
Pattern
Polynomial
PRBS-31
X
31
+x
28
+1
PRBS-9
X
9
+x
5
+1
PRBS-23
X
23
+x
18
+1
PRBS-7
X
7
+x
6
+1
Pseudo-Random Pattern Generator
The pseudo-random pattern generator is specifically designed for the 10GBASE-R and 1588 protocols. To
enable this pattern generator, write the following bits:
• Write 1'b0 to the
TX Test Pattern Select
bit.
• Write 1'b1 to the
TX Test Enable
bit.
UG-01080
2015.01.19
10G PCS Pattern Generators
14-45
Arria V GZ Transceiver Native PHY IP Core
Altera Corporation