Altera Transceiver PHY IP Core User Manual
Page 699
Date
Document
Version
Changes Made
Migrating from Stratix IV to Stratix V
May 2011
1.2
• Added discussion of dynamic reconfiguration for Stratix IV and
Stratix V devices.
• Added information on loopback modes for Stratix IV and Stratix
V devices.
• Added new parameters for Custom PHY IP Core in Stratix V
devices.
All Chapters
December 2010
1.11
• Corrected frequency range for the
phy_mgmt_clk
for the
Custom PHY IP Core in Avalon-MM PHY Management
Interface.
• Added optional
reconfig_from_xcvr[67:0]
to XAUI Top-
Level Signals—Soft PCS and PMA. Provided more detail on size
of
reconfig_from_xcvr
in Dynamic Reconfiguration Interface
Arria II GX, Cyclone IV GX, HardCopy IV GX, and Stratix IV
GX devices.
• Removed table providing ordering codes for the Interlaken PHY
IP Core. Ordering codes are not required for Stratix V devices
using the hard implementation of the Interlaken PHY.
• Added note to 10GBASE-R release information table stating that
“No ordering codes or license files are required for Stratix V
devices.”
• Minor update to the steps to reconfigure a TX or RX PMA
setting in the Transceiver Reconfiguration Controller chapter.
Introduction
December 2010
1.1
• Revised reset diagram.
• Added block diagram for reset.
• Removed support for SOPC Builder.
Getting Started
December 2010
1.1
• Removed description of SOPC Builder design flow. SOPC
Builder is not supported in this release.
10GBASE-R PHY Transceiver
UG-01080
2015.01.19
Revision History for Previous Releases of the Transceiver PHY IP Core
21-39
Additional Information for the Transceiver PHY IP Core
Altera Corporation