Altera Transceiver PHY IP Core - Manual (Page 609)

Description
Specifies the CDR bandwidth preset setting
Options
• Auto
• Low
• Medium
• High
Assign To
PLL instance
master_ch_number
Pin Planner and Assignment Editor Name
Parameter (Assignment Editor Only)
Description
For the PHY IP Core for PCI Express (PIPE), specifies the channel number of the channel acting as the
master channel for a single transceiver bank or 2 adjacent banks. This setting allows you to override the
default master channel assignment for the PCS and PMA. The master channel must use a TX PLL that is
in the same transceiver bank. Available for Gen1, Gen2, and Gen3 variants.
Example: set_parameter -name master_ch_number 4 -to
".pcie_i|altera_xcvr_pipe:_inst|
sv_xcvr_pipe_nr:pipe_nr_inst|sv_xcvr_pipe_native:
transceiver_core"
Options
1, 4
Assign To
Include in .qsf file
Related Information
Transceiver Configurations in Arria V GZ Devices
Refer to Advance [SIC] Channel Placement Guidelines for PIPE Configurations in this document.
PLL_BANDWIDTH_PRESET
Pin Planner and Assignment Editor Name
PLL Bandwidth Preset
Description
Specifies the PLL bandwidth preset setting
UG-01080
2015.01.19
master_ch_number 19-15
Analog Parameters Set Using QSF Assignments Altera Corporation
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