Altera Transceiver PHY IP Core - Manual (Page 14)

Figure 1-2: Stratix V Transceiver Native PHY IP Core
PLLs
PMA
altera _xcvr_native_
Transceiver Native PHY
Transceiver
Reconfiguration
Controller
Reconfiguration to XCVR
Reconfiguration from XCVR
TX and RX Resets
Calilbration Busy
PLL and RX Locked
RX PCS Parallel Data
TX PCS Parallel Data
CDR Reference Clock
(when neither PCS is enabled)
TX PLL Reference Clock
Serializer/
Clock
Generation
Block
RX Serial Data
to
FPGA fabric
Transceiver
PHY Reset
Controller
TX PMA Parallel Data
RX PMA Parallel Data
TX Serial Data
Serializer
Deserializer
Standard
PCS
(optional)
10G PCS
(optional)
As shown, the Stratix V Native PHY connects to the separately instantiated Transceiver Reconfiguration
Controller and Transceiver PHY Reset Controller.
Table 1-1: Native Transceiver PHY Datapaths
Datapaths Stratix V Arria V Arria V GZ Cyclone V
PMA Direct:
This datapath connects the
FPGA fabric directly to the
PMA, minimizing latency.
You must implement any
required PCS functions in the
FPGA fabric.
(1)
Yes Yes Yes -
(1) PMA Direct mode is supported for Arria V GT, ST, and GZ devices, and for Stratix V GT devices only.
UG-01080
2015.01.19
Native Transceiver PHYs 1-3
Introduction to the Protocol-Specific and Native Transceiver PHYs Altera Corporation
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