Transceiver reconfiguration controller memory map – Altera Transceiver PHY IP Core User Manual
Page 529
Signal Name
Direction
Description
reconfig_mgmt_read
Input
Read signal. Active high.
Related Information
Transceiver Reconfiguration Controller Memory Map
Each register-based feature has its own Avalon-MM address space within the Transceiver Reconfiguration
Controller.
Figure 16-3: Memory Map of the Transceiver Reconfiguration Controller Registers
Direct Addressing
Address Offset
0x00
0x13
0x0B
0x1B
0x2B
0x33
0x3B
0x43
0x48
0x7F
Transceiver Reconfiguration Controller
Avalon-MM Interface
reconfig_mgmt_*
Avalon-MM
Registers
Signal Integrity
Features
DFE
ADCE
ATX
Tuning
MIF
Streamer
PLL
Reconfig
EyeQ
PMA
Analog
DCD
Calibration
EyeQ
. . .
DFE
. . .
PMA
ADCE
. . .
ATX
. . .
Streamer
. . .
PLL
DCD
. . .
S
M
Embedded
Controller
. . .
. . .
16-12
Transceiver Reconfiguration Controller Memory Map
UG-01080
2015.01.19
Altera Corporation
Transceiver Reconfiguration Controller IP Core Overview
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)