Altera Transceiver PHY IP Core User Manual
Page 281
Name
Value
Description
Enable embedded reset
controller
On/ Off
When you turn this option On, the embedded reset
controller handles reset of the TX and RX channels at
power up. If you turn this option Off, you must
design a reset controller that manages the following
reset signals:
tx_digitalreset
,
tx_analogreset
,
tx_cal_busy
,
rx_digitalreset
,
rx_analogreset
,
and
rx_cal_busy
. You may also use the Transceiver
PHY Reset Controller to reset the transceivers. For
more information, refer to the Transceiver Reconfigu‐
ration Controller IP Core.
Related Information
•
Transceiver Reconfiguration Controller IP Core Overview
•
•
•
PLL Reconfiguration Parameters for Deterministic Latency PHY
The section describes the PLL Reconfiguration options for the Deterministic Latency PHY IP core.
This table lists the PLL Reconfiguration options. For more information about transceiver reconfiguration
registers, refer to PLL Reconfiguration.
Table 11-8: PLL Reconfiguration Options
Name
Value
Description
Allow PLL/CDR Reconfiguration On/Off
You must enable this option if you plan to
reconfigure the PLLs in your design. This option
is also required to simulate PLL reconfiguration.
Number of TX PLLs
Device
dependent
Specifies the number of TX PLLs that can be used
to dynamically reconfigure channels to run at
multiple data rates. If your design does not
require transceiver TX PLL dynamic reconfigura‐
tion, set this value to 1. The number of actual
physical PLLs that are implemented depends on
the selected clock network. Each channel can
dynamically select between n PLLs, where n is the
number of PLLs specified for this parameter.
Note: For more details, refer to the
Transceiver Clocking chapter in the
device handbook for the device family
you are using.
UG-01080
2015.01.19
PLL Reconfiguration Parameters for Deterministic Latency PHY
11-13
Deterministic Latency PHY IP Core
Altera Corporation