Dynamic reconfiguration for stratix v native phy – Altera Transceiver PHY IP Core User Manual
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Example 12-2: Using the max_delay Constraint to Identify Asynchronous Inputs
You can use the set_max_delay constraint on a given path to create a constraint for asynchronous
signals that do not have a specific clock relationship but require a maximum path delay. The
following example illustrates this approach.
# Example: Apply 10ns max delay
set_max_delay -from *tx_from_fifo* -to *8g*pcs*SYNC_DATA_REG1 10
Example 12-3: Using the set_false TimeQuest Constraint to Identify Asynchronous Inputs
You can use the set_false path command only during Timequest timing analysis. The following
example illustrates this approach.
#if {$::TimeQuestInfo(nameofexecutable) eq "quartus_fit"} {
#} else {
#set_false_path -from [get_registers {*tx_from_fifo*}] -through
{*txbursten*} -to [get_registers *8g_*_pcs*SYNC_DATA_REG
Dynamic Reconfiguration for Stratix V Native PHY
Dynamic reconfiguration calibrates each channel to compensate for variations due to process, voltage,
and temperature (PVT).
As silicon progresses towards smaller process nodes, circuit performance is affected more by variations
due to PVT. These process variations result in analog voltages that can be offset from required ranges. The
calibration performed by the dynamic reconfiguration interface compensates for variations due to PVT.
For more information about transceiver reconfiguration refer to Chapter 16, Transceiver Reconfiguration
Controller IP Core.
Example 12-4: Informational Messages for the Transceiver Reconfiguration Interface
For non-bonded clocks, each channel and each TX PLL has a separate dynamic reconfiguration
interfaces. The MegaWizard Plug-In Manager provides informational messages on the
connectivity of these interfaces. The following example shows the messages for the Stratix V
Native PHY with four duplex channels, four TX PLLs, in a non-bonded configuration.
PHY IP will require 8 reconfiguration interfaces for connection to the
external reconfiguration controller.
Reconfiguration interface offsets 0-3 are connected to the transceiver
channels.
Reconfiguration interface offsets 4–7 are connected to the transmit PLLs.
UG-01080
2015.01.19
Dynamic Reconfiguration for Stratix V Native PHY
12-75
Stratix V Transceiver Native PHY IP Core
Altera Corporation