Daisy-chain interface signals, Daisy-chain interface signals -27 – Altera Transceiver PHY IP Core User Manual
Page 83
Signal Name
Direction
Description
rx_latency_adj_10g[15:0]
Output
When you enable 1588, this signal outputs the real
time latency in XGMII clock cycles (156.25 MHz)
for the RX PCS and PMA datapath for 10G mode.
Bits 0 to 9 represent the fractional number of clock
cycles. Bits 10 to 15 represent the number of clock
cycles.
tx_latency_adj_10g[15:0]
Output
When you enable 1588, this signal outputs real time
latency in XGMII clock cycles (156.25 MHz) for the
TX PCS and PMA datapath for 10G mode. Bits 0 to
9 represent the fractional number of clock cycles.
Bits 10 to 15 represent the number of clock cycles.
rx_data_ready
Output
When asserted, indicates that the MAC can begin
sending data to the 10GBASE-KR PHY IP Core.
tx_frame
Output
Asynchronous status flag output of the TX FEC
module. When asserted, indicates the beginning of
the generated 2112-bit FEC frame.
rx_clr_counters
Input
When asserted, resets the status counters in the RX
FEC module. This is an asynchronous input.
rx_frame
Output
Asynchronous status flag output of the RX FEC
module. When asserted, indicates the beginning of a
2112-bit received FEC frame.
rx_block_lock
Output
Asynchronous status flag output of the RX FEC
module. When asserted, indicates successful FEC
block lock.
rx_parity_good
Output
Asynchronous status flag output of the RX FEC
module. When asserted, indicates that the parity
calculation is good for the current received FEC
frame. Used in conjunction with the
rx_frame
signal.
rx_parity_invalid
Output
Asynchronous status flag output of the RX FEC
module. When asserted, indicates that the parity
calculation is not good for the current received FEC
frame. Used in conjunction with the
rx_frame
signal.
rx_error_corrected
Output
Asynchronous status flag output of the RX FEC
module. When asserted, indicates that an error was
found and corrected in the current received FEC
frame. Used in conjunction with the
rx_frame
signal.
Daisy-Chain Interface Signals
The optional daisy-chain interface signals connect link partners using a daisy-chain topology.
UG-01080
2015.01.19
Daisy-Chain Interface Signals
4-27
Backplane Ethernet 10GBASE-KR PHY IP Core with Early Access FEC Option
Altera Corporation