Altera Transceiver PHY IP Core - Manual (Page 70)

Auto negotiation with XAUI is not supported. Auto negotiation is run upon power up or if the auto
negotiation module is reset.
The following figures illustrate the handshaking between the Auto Negotiation, Link Training, Sequencer
and Transceiver Reconfiguration Controller blocks. Reconfig controller should use
lt_start_rc
signal in
combination with
main_rc
,
post_rc
,
pre_rc
, and
tap_to_upd
to change TX equalization settings.
Figure 4-5: Transition from Auto Negotiation to Link Training Mode
pcs_mode_rc[5:0]
lt_start_rc
rc_busy
seq_start_rc
tap_to_upd[2:0]
main_rc[5:0]
post_rc[4:0]
pre_rc[3:0]
010
29 28 27
52
30
5
init state
02 01
The Transceiver Reconfiguration Controller uses
seq_start_rc
in combination with the
pcs_mode_rc
value to initiate a change to Auto Negotiation mode or from Link Training mode to 10GBASE-KR Data
mode. After TX equalization completes, this timing diagram shows the transition from Link Training
mode to 10GBASE-KR Data mode and MIF streaming.
Figure 4-6: Transition from Link Training to Data Mode
pcs_mode_rc[5:0]
lt_start_rc
seq_start_rc
MIF streaming
rc_busy
tap_to_upd[2:0]
main_rc[5:0]
post_rc[4:0]
pre_rc[3:0]
04
5
9
42
001
02
Related Information
Changing Transceiver Settings Using Streamer-Based Reconfiguration on page 16-43
10GBASE-KR PHY Arbitration Logic Requirements
This topic describes the arbitration functionality that you must implement.
The arbiter should implement the following logic. You can modify this logic based on your system
requirements:
1. Accept requests from either the Sequencer or Link Training block. Prioritize requests to meet system
requirements. Requests should consist of the following two buses:
4-14 10GBASE-KR PHY Arbitration Logic Requirements
UG-01080
2015.01.19
Altera Corporation Backplane Ethernet 10GBASE-KR PHY IP Core with Early Access FEC Option
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