Speed detection parameters, Phy analog parameters, 10gbase-kr phy ip core functional description – Altera Transceiver PHY IP Core User Manual
Page 66: Speed detection parameters -10, Phy analog parameters -10, 10gbase-kr phy ip core functional description -10
Speed Detection Parameters
Selecting the speed detection option gives the PHY the ability to detect to link partners that support 1G/
10GbE but have disabled Auto-Negotiation. During Auto-Negotiation, if AN cannot detect Differential
Manchester Encoding (DME) pages from a link partner, the Sequencer reconfigures to 1GE and 10GE
modes (Speed/Parallel detection) until it detects a valid 1G or 10GbE pattern.
Table 4-9: Speed Detection
Parameter Name
Options
Description
Enable automatic speed detection On
Off
When you turn this option On, the core includes
the Sequencer block that sends reconfiguration
requests to detect 1G or 10GbE when the Auto
Negotiation block is not able detect AN data.
Avalon-MM clock frequency
100-125 MHz
Specifies the clock frequency for
phy_mgmt_clk
.
Link fail inhibit time for 10Gb
Ethernet
504 ms
Specifies the time before
link_status
is set to
FAIL or OK. A link fails if the
link_fail_
inhibit_time
has expired before
link_status
is set to OK. The legal range is 500-510 ms. For
more information, refer to "Clause 73 Auto
Negotiation for Backplane Ethernet" in IEEE Std
802.3ap-2007.
Link fail inhibit time for 1Gb
Ethernet
40-50 ms
Specifies the time before
link_status
is set to
FAIL or OK . A link fails if the link_fail_inhibit_
time has expired before
link_status
is set to
OK. The legal range is 40-50 ms.
PHY Analog Parameters
You can specify analog parameters using the Quartus II Assignment Editor, the Pin Planner, or the
Quartus II Settings File (.qsf).
Related Information
•
Analog Settings for Arria V GZ Devices
on page 19-11
•
Analog PCB Settings for Stratix V Devices
on page 19-34
10GBASE-KR PHY IP Core Functional Description
This topic provides high-level block diagram of the 10GBASE-KR hardware.
The following figure shows the 10GBASE-KR PHY IP Core and the supporting modules required for
integration into your system.
4-10
Speed Detection Parameters
UG-01080
2015.01.19
Altera Corporation
Backplane Ethernet 10GBASE-KR PHY IP Core with Early Access FEC Option