Altera Transceiver PHY IP Core User Manual
Page 58
Figure 4-1: 10GBASE-KR PHY MegaCore Function and Supporting Blocks
Altera Device with 10.3125+ Gbps Serial Transceivers
10GBASE-KR PHY MegaCore Function
Native PHY Hard IP
TX
Serial
Data
RX
Serial
Data
Copper
Backplane
322.265625 MHz
or 644.53125 MHz
Reference Clock
62.5 MHz or 125 MHz
Reference Clock
Legend
Hard IP
Soft IP
ATX/CMU
TX PLL
For
10 GbE
ATX/CMU
TX PLL
For 1 GbE
1.25 Gb/
10.3125 Gb
Hard PMA
Link
Status
10 Gb
Ethernet
Hard PCS
1 Gb
Ethernet
Standard
Hard PCS
To/From Modules in the PHY MegaCore
Control and Status
Registers
Avalon-MM
PHY Management
Interface
PCS Reconfig
Request
PMA Reconfig
Request
Optional
1588 TX and
RX Latency
Adjust 1G
and 10G
To/From
1G/10Gb
Ethernet
MAC
RX GMII Data
TX GMII Data
@ 125 MHz
RX XGMII Data
TX XGMII Data
@156.25 MHz
1 GIGE
PCS
10GBASE-KR
Auto-Negotiation
10GBASE-KR
Link Training
Soft 10G PCS &
FEC
Sequencer
The Backplane Ethernet 10GBASE-KR PHY IP Core includes the following new modules to enable
operation over a backplane:
• Link Training (LT)— The LT mechanism allows the 10GBASE-KR PHY to automatically configure the
link-partner TX PMDs for the lowest Bit Error Rate (BER). LT is defined in Clause 72 of IEEE Std
802.3ap-2007.
• Auto negotiation (AN)—The Altera 10GBASE-KR PHY IP Core can auto-negotiate between
1000BASE-KX (1GbE) and 10GBASE-KR (10GbE) PHY types. The AN function is mandatory for
Backplane Ethernet. It is defined in Clause 73 of the IEEE Std 802.3ap-2007.
• Forward Error Correction—Forward Error Correction (FEC) function is an optional feature defined in
Clause 74 of IEEE 802.3ap-2007. It provides an error detection and correction mechanism allowing
noisy channels to achieve the Ethernet-mandated Bit Error Rate (BER) of 10
-12
.
Related Information
4-2
Backplane Ethernet 10GBASE-KR PHY IP Core with Early Access FEC Option
UG-01080
2015.01.19
Altera Corporation
Backplane Ethernet 10GBASE-KR PHY IP Core with Early Access FEC Option