Altera Transceiver PHY IP Core - Manual (Page 191)

• Stratix V Hard IP for PCI Express IP Core User Guide
• Transceiver Configurations in Arria V GZ Devices or Transceiver Configurations in Stratix V
Devices
PHY for PCIe (PIPE) Device Family Support
IP cores provide either final or preliminary support for target Altera device families. These terms have the
following definitions:
• Final support—Verified with final timing models for this device.
• Preliminary support—Verified with preliminary timing models for this device.
Table 8-1: Device Family Support
Device Family Support
Arria V GZ devices–Hard PCS + PMA Final
Arria V GX, GT, SX, and ST devices - Hard PCS +
PMA
Final
Stratix V devices–Hard PCS + PMA Final
Other device families No support
PHY for PCIe (PIPE) Resource Utilization
This section describes PIPE resource utilization.
Because the PHY IP Core for PCI Express is implemented in hard logic it uses less than 1% of the
available adaptive logic modules (ALMs), memory, primary and secondary logic registers.
Parameterizing the PHY IP Core for PCI Express (PIPE)
Complete the following steps to configure the PHY IP Core for PCI Express in the MegaWizard Plug-In
Manager:
1. Under Tools > IP Catalog, select the device family of your choice.
2. Under Tools > IP Catalog >Interfaces > PCI Express, selectPHY IP Core for PCI Express (PIPE).
3. Use the tabs on the MegaWizard Plug-In Manager to select the options required for the protocol.
4. Refer to the General Options Parameters to learn more about the parameters.
5. Click Finish to generate your customized PHY IP Core for PCI Express variant.
PHY for PCIe (PIPE) General Options Parameters
This section describes the PHY IP Core for PCI Express parameters, which you can set using the
MegaWizard Plug-In Manager; the settings are available on the General Options tab.
UG-01080
2015.01.19
PHY for PCIe (PIPE) Device Family Support 8-3
PHY IP Core for PCI Express (PIPE) Altera Corporation
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