Altera Transceiver PHY IP Core - Manual (Page 520)

Figure 16-1: Transceiver Reconfiguration Controller
to and from
Embedded
Controller
TX and RX
Serial Data
Avalon-MM master interface
Transceiver
Reconfiguration
Controller
S
M Avalon-MM slave interface S
reconfig_to_xcvr[ :0]
reconfig_mif_address[31:0]
reconfig_mif_read
Reconfiguration
Management
Interface
reconfig_mif_readdata[15:0]
reconfig_mif_waitrequest
Streaming Data
reconfig_from_xcvr[ :0]
Transceiver PHY
Registers to
reconfigure
User Application
Including MAC
Altera V-Series FPGA
.
.
.
.
.
.
S
M Master
M
S
MIF
ROM
An embedded controller programs the Transceiver Reconfiguration Controller using its Avalon-MM
slave interface. The
reconfig_to_xcvr
and
reconfig_from_xcvr
buses include the Avalon-MM address,
read, write, readdata, writedata, and signals that connect to features related to calibration and signal
integrity.
UG-01080
2015.01.19
Transceiver Reconfiguration Controller System Overview 16-3
Transceiver Reconfiguration Controller IP Core Overview Altera Corporation
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