Altera Transceiver PHY IP Core - Manual (Page 543)

Table 16-16: AEQ Offsets and Values
Offset Bits R/W Register Name Description Default Value
0x0
[8] R
adapt_done
When asserted, indicates that adaptation has
completed. In One-Time Adaptation Mode,
AEQ stops searching new EQ settings even if
the signal quality of incoming serial data is
inadequate.
For some extreme cases, when the channel loss
is too much for AEQ to compensate, the
adapt_done
signal may never be asserted. The
AEQ engine can take up to 50,000 reconfigura‐
tion clock cycles before selecting the final
equalization settings.
1b’0
[1:0] RW
mode Specifies the following address modes:
• 2’b00: Low power manual equalization
mode
• 2’b01: One-time AEQ adaptation at power
up
• 2’b11: Reserved
2’b00
0x1 [3:0] R
equalization
results
This is the value set by the automatic AEQ
adaptation performed at startup. If you choose
to perform manual equalization using the
linear equalizer, you can use this value as a
reference. Although automatic and manual
equalization do not provide identical
functionality, specifying this value enables
manual equalization to approximate the
original setting.
4’b0000
Refer to Changing Transceiver Settings Using Register-Based Reconfiguration for the procedures you can
use to control AEQ.
Transceiver Reconfiguration Controller ATX PLL Calibration Registers
The ATX PLL Calibration registers allow you to rerun ATX calibration after power up. The Transceiver
Reconfiguration Controller automatically runs ATX calibration at power up.
Note: You may need to rerun ATX calibration if you reset an ATX PLL and it does not lock after the
specified lock time.
The following table lists the direct access ATX registers that you can access using Avalon-MM reads and
writes on reconfiguration management interface.
Note: All undefined register bits are reserved.
16-26 Transceiver Reconfiguration Controller ATX PLL Calibration Registers
UG-01080
2015.01.19
Altera Corporation Transceiver Reconfiguration Controller IP Core Overview
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