Altera Transceiver PHY IP Core User Manual
Page 79
10GBASE-KR GMII Data Interface
gmii_rx_err
Output
When asserted, indicates an error. May be asserted
at any time during a frame transfer to indicate an
error in that frame.
gmii_rx_dv
Output
When asserted, indicates the start of a new frame. It
remains asserted until the last byte of data on the
frame is present on
gmii_rx_d
.
led_char_err
Output
10-bit character error. Asserted for one
rx_clkout_
1g
cycle when an erroneous 10-bit character is
detected
led_link
Output
When asserted, indicates successful link synchroni‐
zation.
led_disp_err
Output
Disparity error signal indicating a 10-bit running
disparity error. Asserted for one
rx_clkout_1g
cycle when a disparity error is detected. A running
disparity error indicates that more than the
previous and perhaps the current received group
had an error.
led_an
Output
Clause 37 Auto-Negotiation status. The PCS
function asserts this signal when Auto-Negotiation
completes.
10GBASE-KR PHY XGMII Mapping to Standard SDR XGMII Data
The 72-bit TX XGMII data bus format is different than the standard SDR XGMII interface. The following
table lists the mapping of this non-standard format to the standard SDR XGMII interface.
Table 4-12: TX XGMII Mapping to Standard SDR XGMII Interface
Signal Name
SDR XGMII Signal Name
Description
xgmii_tx_dc[7:0]
xgmii_sdr_data[7:0]
Lane 0 data
xgmii_tx_dc[8]
xgmii_sdr_ctrl[0]
Lane 0 control
xgmii_tx_dc[16:9]
xgmii_sdr_data[15:8]
Lane 1 data
xgmii_tx_dc[17]
xgmii_sdr_ctrl[1]
Lane 1 control
xgmii_tx_dc[25:18]
xgmii_sdr_data[23:16]
Lane 2 data
xgmii_tx_dc[26]
xgmii_sdr_ctrl[2]
Lane 2 control
xgmii_tx_dc[34:27]
xgmii_sdr_data[31:24]
Lane 3 data
xgmii_tx_dc[35]
xgmii_sdr_ctrl[3]
Lane 3 control
xgmii_tx_dc[43:36]
xgmii_sdr_data[39:32]
Lane 4 data
xgmii_tx_dc[44]
xgmii_sdr_ctrl[4]
Lane 4 control
UG-01080
2015.01.19
10GBASE-KR PHY XGMII Mapping to Standard SDR XGMII Data
4-23
Backplane Ethernet 10GBASE-KR PHY IP Core with Early Access FEC Option
Altera Corporation