Altera Transceiver PHY IP Core - Manual (Page 2)

Contents
Introduction to the Protocol-Specific and Native Transceiver PHYs............... 1-1
Protocol-Specific Transceiver PHYs......................................................................................................... 1-1
Native Transceiver PHYs ...........................................................................................................................1-2
Non-Protocol-Specific Transceiver PHYs................................................................................................1-4
Transceiver PHY Modules..........................................................................................................................1-4
Transceiver Reconfiguration Controller...................................................................................................1-5
Resetting the Transceiver PHY.................................................................................................................. 1-5
Running a Simulation Testbench.............................................................................................................. 1-6
Unsupported Features.................................................................................................................................1-9
Getting Started Overview....................................................................................2-1
Installation and Licensing of IP Cores......................................................................................................2-1
Design Flows.................................................................................................................................................2-2
MegaWizard Plug-In Manager Flow.........................................................................................................2-3
Specifying Parameters..................................................................................................................... 2-3
Simulate the IP Core........................................................................................................................2-4
10GBASE-R PHY IP Core................................................................................... 3-1
10GBASE-R PHY Release Information.................................................................................................... 3-6
10GBASE-R PHY Device Family Support................................................................................................3-6
10GBASE-R PHY Performance and Resource Utilization for Stratix IV Devices..............................3-7
10GBASE-R PHY Performance and Resource Utilization for Arria V GT Devices.......................... 3-7
10GBASE-R PHY Performance and Resource Utilization for Arria V GZ and Stratix V
Devices..................................................................................................................................................... 3-8
Parameterizing the 10GBASE-R PHY.......................................................................................................3-8
General Option Parameters........................................................................................................................3-9
Analog Parameters for Stratix IV Devices..............................................................................................3-12
10GBASE-R PHY Interfaces.....................................................................................................................3-13
10GBASE-R PHY Data Interfaces........................................................................................................... 3-14
10GBASE-R PHY Status, 1588, and PLL Reference Clock Interfaces................................................3-17
Optional Reset Control and Status Interface......................................................................................... 3-18
10GBASE-R PHY Clocks for Arria V GT Devices................................................................................3-19
10GBASE-R PHY Clocks for Arria V GZ Devices................................................................................3-20
10GBASE-R PHY Clocks for Stratix IV Devices...................................................................................3-21
10GBASE-R PHY Clocks for Stratix V Devices.....................................................................................3-22
10GBASE-R PHY Register Interface and Register Descriptions.........................................................3-23
10GBASE-R PHY Dynamic Reconfiguration for Stratix IV Devices................................................. 3-28
10GBASE-R PHY Dynamic Reconfiguration for Arria V and Stratix V Devices.............................3-29
1588 Delay Requirements.........................................................................................................................3-30
10GBASE-R PHY TimeQuest Timing Constraints.............................................................................. 3-30
10GBASE-R PHY Simulation Files and Example Testbench.............................................................. 3-32
TOC-2 Altera Transceiver PHY IP Core User Guide
Altera Corporation