beautypg.com

Altera Transceiver PHY IP Core User Manual

Page 647

background image

Migrating from Stratix IV to Stratix V Devices

Overview

20

2013.12.20

UG-01080

Subscribe

Send Feedback

Previously, Altera provided the ALTGX megafunction as a general purpose transceiver PHY solution. The

current release of the Quartus II software includes protocol-specific PHY IP cores that simplify the

parameterization process.
The design of these protocol-specific transceiver PHYs is modular and uses standard interfaces. An

Avalon-MM interface provides access to control and status registers that record the status of the PCS and

PMA modules. Consequently, you no longer must include signals in the top level of your transceiver PHY

to determine the status of the serial RX and TX interfaces. Using standard interfaces to access this device-

dependent information should ease future migrations to other device families and reduce the overall

design complexity. However, to facilitate debugging, you may still choose to include some device-

dependent signals in the top level of your design during the initial simulations or even permanently. All

protocol-specific PHY IP in Stratix V devices also include embedded controls for post-reset initialization

which are available through the Avalon-MM interface.
For Stratix IV devices, the location of the transceiver dynamic reconfiguration logic is design dependent.

In general, reconfiguration logic is integrated with the transceiver channels for simple configurations and

is separately instantiated for more complex designs that use a large number of channels or instantiate

more than one protocol in a single transceiver quad. For Stratix V devices, transceiver dynamic reconfigu‐

ration is always performed using the separately instantiated Transceiver Reconfiguration Controller.
Control of loopback modes is also different in Stratix IV and Stratix V devices. For Stratix IV devices, you

must select loopback options in the using the MegaWizard Plug-In Manager. For Stratix V devices, you

control loopback modes through Avalon-MM registers.

Table 20-1: Controlling Loopback Modes in Stratix IV and Stratix V Devices

Loopback Mode

Stratix IV

Stratix V

Serial loopback

On the Loopback tab of the

ALTGX MegaWizard Plug-In

Manager, Instantiate the

rx_

seriallpbken

signal by selecting

the Serial loopback option. Drive

this signal to 1 to put the

transceiver in serial loopback

mode.

Use the Avalon-MM PHY

management interface to set the

appropriate bit in the

phy_serial_

loopback

register (0x061).

©

2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are

trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as

trademarks or service marks are the property of their respective holders as described at

www.altera.com/common/legal.html

. Altera warrants performance

of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any

products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,

product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device

specifications before relying on any published information and before placing orders for products or services.

ISO

9001:2008

Registered

www.altera.com

101 Innovation Drive, San Jose, CA 95134