Altera Transceiver PHY IP Core User Manual
Page 651
Differences Between XAUI PHY Ports in Stratix IV and Stratix V Devices
This section lists the differences between the top-level signals in Stratix IV GX and Stratix V GX/GS
devices.
Table 20-3: Correspondences between XAUI PHY Stratix IV GX and Stratix V Device Signals
Stratix IV GX Devices
(20)
Stratix V Devices
Signal Name
Width
Signal Name
Width
Reference Clocks and Resets
pll_inclk
1
refclk
1
rx_cruclk
[<n> -1:0]
Not available
—
coreclkout
1
xgmii_rx_clk
1
rx_coreclk
[<n> -1:0]
Not available
—
tx_coreclk
[<n> -1:0]
xgmii_tx_clk
1
Not available
—
rx_pma_ready
1
Not available
—
tx_pma_ready
1
Data Ports
rx_datain
[<n> -1:0]
xaui_rx_serial
[3:0]
tx_datain
[16<n> -1:0]
xgmii_tx_dc
[63:0]
rx_dataout
[16<n> -1:0]
xgmii_rx_dc
[63:0]
tx_dataout
[<n> -1:0]
xaui_tx_serial
[3:0]
Optional TX and RX Status Ports
gxb_powerdown
[<n>/4 -1:0]
Not available, however
you can access them
through the Avalon-MM
PHY management
interface.
—
pll_locked
[<n> -1:0]
Not available
—
rx_locktorefclk
[<n> -1:0]
Not available
—
rx_locktodata
[<n> -1:0]
Not available
—
rx_pll_locked
[<n>/4 -1:0]
Not available
—
rx_freqlocked
[<n>/4 -1:0]
Not available
—
rx_phase_comp_fifo_error
[<n>/4 -1:0]
Not available
—
tx_phase_comp_fifo_error
[<n>/4 -1:0]
Not available
—
(20)
<n> = the number of lanes. <d> = the total deserialization factor from the pin to the FPGA fabric.
UG-01080
2013.12.20
Differences Between XAUI PHY Ports in Stratix IV and Stratix V Devices
20-5
Migrating from Stratix IV to Stratix V Devices Overview
Altera Corporation