Altera Phase-Locked Loop Reconfiguration IP Core User Manual
Features
February 2012
Altera Corporation
UG-032405-6.0
User Guide
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Phase-Locked Loop Reconfiguration
(ALTPLL_RECONFIG) Megafunction
This user guide describes the features and behavior of the ALTPLL_RECONFIG
megafunction that you can configure through the parameter editor in the Quartus
®
II
software.
f
This user guide assumes that you are familiar with megafunctions and how to create
them. If you are unfamiliar with Altera megafunctions or the parameter editor, refer
to the
Phase-locked loops (PLLs) use divide counters and voltage-controlled oscillator
(VCO) phase taps to perform frequency synthesis and phase shifts. In enhanced and
fast PLLs, you can reconfigure the counter settings as well as phase shift the PLL
output clock in real time. You can also change the charge-pump and loop-filter
components, which dynamically affect the PLL bandwidth. The ALTPLL_RECONFIG
megafunction implements reconfiguration logic to facilitate dynamic real-time
reconfiguration of PLLs in Altera devices. You can use the megafunction to update the
output clock frequency, PLL bandwidth, and phase shifts in real time, without
reconfiguring the entire FPGA.
Features
The ALTPLL_RECONFIG megafunction offers the following additional features to the
ALTPLL megafunction:
■
Reconfiguration of pre-scale counter (N) parameters.
■
Reconfiguration of feedback counter (M)
parameters.
■
Reconfiguration of post-scale output counter (C) parameters.
■
Reconfiguration of delay element or phase shift of each counter. For Stratix
®
III,
Stratix IV, Cyclone
®
III, Cyclone IV, HardCopy
®
III, HardCopy IV, and
Arria
®
II GX devices, use the ALTPLL megafunction to access this feature.
■
Dynamic adjustment of the charge-pump current and loop-filter components to
facilitate dynamic reconfiguration of the PLL bandwidth. This feature is available
only in Arria GX, HardCopy II, Stratix II, Stratix II GX, Stratix III, and Stratix IV
devices.
■
Reconfiguration from multiple configuration files using external read-only
memory (ROM) in user mode. This feature is available only in Stratix III, Stratix IV,
Cyclone III, Cyclone IV, and Arria II GX devices. The ALTPLL_RECONFIG
supports reconfiguration from Memory Initialization File (.mif) and Hexadecimal
File (.hex).
Document Outline
- Phase-Locked Loop Reconfiguration (ALTPLL_RECONFIG) Megafunction
- Features
- Common Applications
- Device Family Support
- Resource Utilization and Performance
- Parameter Settings
- Checking Design Violations With the Design Assistant
- Simulation
- Functional Description—Implementing Multiple Reconfiguration Using an External ROM
- Design Example
- Specifications
- Document Revision History