Altera Transceiver PHY IP Core User Manual
Page 41
Signal Name
XGMII Signal Name
Description
xgmii_tx_dc_[44]
xgmii_sdr_ctrl[4]
Lane 4 control
xgmii_tx_dc_[52:45]
xgmii_sdr_data[47:40]
Lane 5 data
xgmii_tx_dc_[53]
xgmii_sdr_ctrl[5]
Lane 5 control
xgmii_tx_dc_[61:54]
xgmii_sdr_data[55:48]
Lane 6 data
xgmii_tx_dc_[62]
xgmii_sdr_ctrl[6]
Lane 6 control
xgmii_tx_dc_[70:63]
xgmii_sdr_data[63:56]
Lane 7 data
xgmii_tx_dc_[71]
xgmii_sdr_ctrl[7]
Lane 7 control
Table 3-12: Mapping from XGMII RX Bus to the XGMII SDR Bus
Signal Name
XGMII Signal Name
Description
xgmii_rx_dc_[7:0]
xgmii_sdr_data[7:0]
Lane 0 data
xgmii_rx_dc_[8]
xgmii_sdr_ctrl[0]
Lane 0 control
xgmii_rx_dc_[16:9]
xgmii_sdr_data[15:8]
Lane 1 data
xgmii_rx_dc_[17]
xgmii_sdr_ctrl[1]
Lane 1 control
xgmii_rx_dc_[25:18]
xgmii_sdr_data[23:16]
Lane 2 data
xgmii_rx_dc_[26]
xgmii_sdr_ctrl[2]
Lane 2 control
xgmii_rx_dc_[34:27]
xgmii_sdr_data[31:24]
Lane 3 data
xgmii_rx_dc_[35]
xgmii_sdr_ctrl[3]
Lane 3 control
xgmii_rx_dc_[43:36]
xgmii_sdr_data[39:32]
Lane 4 data
xgmii_rx_dc_[44]
xgmii_sdr_ctrl[4]
Lane 4 control
xgmii_rx_dc_[52:45]
xgmii_sdr_data[47:40]
Lane 5 data
xgmii_rx_dc_[53]
xgmii_sdr_ctrl[5]
Lane 5 control
xgmii_rx_dc_[61:54]
xgmii_sdr_data[55:48]
Lane 6 data
xgmii_rx_dc_[62]
xgmii_sdr_ctrl[6]
Lane 6 control
xgmii_rx_dc_[70:63]
xgmii_sdr_data[63:56]
Lane 7 data
xgmii_rx_dc_[71]
xgmii_sdr_ctrl[7]
Lane 7 control
10GBASE-R PHY Status, 1588, and PLL Reference Clock Interfaces
This section describes the 10GBASE-R PHY status, 1588, and PLL reference clock interfaces.
UG-01080
2015.01.19
10GBASE-R PHY Status, 1588, and PLL Reference Clock Interfaces
3-17
10GBASE-R PHY IP Core
Altera Corporation