1g/10gbe phy release information, 1g/10gbe phy release information -2 – Altera Transceiver PHY IP Core User Manual
Page 111
Figure 5-1: Level Modules of the 1G/10GbE PHY MegaCore Function
Altera Device with 10.3125+ Gbps Serial Transceivers
1G/10Gb Ethernet PHY MegaCore Function
Native PHY Hard IP
257.8
MHz
40-b
40-b
TX
Serial
Data
RX
Serial
Data
1 Gb SFP /
10 Gb SFP+
or XFP /
1G/10 Gb SFP+
Module/
Standard PHY
Product
1G/ 10 Gb
Ethernet
Network
Interface
322.265625 MHz
or 644.53125 MHz
Reference Clock
62.5 MHz or 125 MHz
Reference Clock
Legend
Hard IP
Soft IP
ATX/CMU
TX PLL
For
10 GbE
ATX/CMU
TX PLL
For 1 GbE
1.25 Gb/
10.3125 Gb
Hard PMA
Link
Status
Sequencer
(Optional)
10 Gb
Ethernet
Hard PCS
1 Gb
Ethernet
Standard
Hard PCS
(Optional)
To/From Modules in the PHY MegaCore
Control and Status
Registers
Avalon-MM
PHY Management
Interface
PCS Reconfig
Request
Optional
1588 TX and
RX Latency
Adjust 1G
and 10G
To/From
1G/10Gb
Ethernet
MAC
RX GMII Data
TX GMII Data
@ 125 MHz
RX XGMII Data
TX XGMII Data
@156.25 MHz
1 GIGE
PCS
An Avalon
®
Memory-Mapped (Avalon-MM) slave interface provides access to the 1G/10GbE PHY IP
Core registers. These registers control many of the functions of the other blocks. Many of these bits are
defined in Clause 45 of IEEE Std 802.3ap
-
2007.
Related Information
•
•
1G/10GbE PHY Release Information
This topic provides information about this release of the 1G/10GbE PHY IP Core.
Table 5-1: 1G/10GbE Release Information
Item
Description
Version
13.1
Release Date
November 2013
Ordering Codes
IP-1G10GBASER PHY (primary)
5-2
1G/10GbE PHY Release Information
UG-01080
2015.01.19
Altera Corporation
1G/10 Gbps Ethernet PHY IP Core