Altera Transceiver PHY IP Core - Manual (Page 602)

1
Assign To
Pin - RX serial data
XCVR_RX_SD_ON
Pin Planner and Assignment Editor Name
Receiver Cycle Count Before Signal Detect Block Declares Presence Of Signal
Description
Number of parallel cycles to wait before the signal detect block declares presence of signal. Only used for
the PCIe PIPE PHY, SATA, and SAS protocols.
Options
0–16
1
Assign To
Pin - RX serial data
XCVR_RX_SD_THRESHOLD
Pin Planner and Assignment Editor Name
Receiver Signal Detection Voltage Threshold
Description
Specifies signal detection voltage threshold level, V
th
. The following encodings are defined:
• SDLV_50MV=7
• SDLV_45MV=6
• SDLV_40MV=5
• SDLV_35MV=4
• SDLV_30MV=3
• SDLV_25MV=2
• SDLV_20MV=1
• SDLV_15MV=0
Only used for the PCIe PIPE PHY, SATA, and SAS protocols.
The signal detect output is high when the receiver peak-to-peak differential voltage (diff p-p) > V
th
x 4.
For example, a setting of 6 translates to peak-to-peak differential voltage of 180mV (4*45mV). The V
diff p-
p
must be > 180mV to turn on the signal detect circuit.
Options
• 0-7
• 3
19-8 XCVR_RX_SD_ON
UG-01080
2015.01.19
Altera Corporation Analog Parameters Set Using QSF Assignments
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